View PI6C2308_293791.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308
3.3V Zero-Delay Buffer
Product Features
* 10 MHz to 134 MHz operating range * Zero input-output propagation delay, adjustable by external capacitive load on FBK input * Multiple configurations, see Available PI6C2308 Configurations table * Input to output delay, less than 200ps * Multiple low skew outputs - Output-output skew less than 200ps - Device-device skew less than 600ps - Two banks of four outputs, Hi-Z by two select inputs * Low Jitter, less than 200ps * 3.3V operation * Space-saving Packages: 16-pin, 150-mil SOIC package (W16) (-1, -1H, -2, -3, -4, -6) 16-pin TSSOP package (L16) (-1, -1H) * Available in industrial and commercial temperatures
Functional Description
Providing two banks of four outputs, the PI6C2308 is a 3.3V zerodelay buffer designed to distribute clock signals in applications including PC, workstation, datacom, telecom, and high-performance systems. Each bank of four outputs can be controlled by the select inputs as shown in the Select Input Decoding Table. The PI6C2308 provides 8 copies of a clock signal that has 200ps phase error compared to a reference clock. The skew between the output clock signals for PI6C2308 is less than 200ps. When there are no rising edges on the REF input, the PI6C2308 enters a power down state. In this mode, the PLL is off and all outputs are Hi-Z. This results in less than 12A of current draw. The Select Input Decoding Table shows additional examples when the PLL shuts down. The PI6C2308 configuration table shows all available devices. The base part, PI6C2308-1, provides output clocks in sync with a reference clock. With faster rise and fall times, the PI6C2308-1H is the high drive version of the PI6C2308-1. Depending on which output drives the feedback pin, PI6C2308-2 provides 2X and 1X clock signals on each output bank. The PI6C2308-3 allows the user to obtain 4X and 2X frequencies on the outputs. The PI6C2308-4 provides 2X clock signals on all outputs. PI6C2308 (-1, -2, -3, -4) allows bank B to be Hi-Z when all output clocks are not required.The PI6C2308-6 allows bank B to switch from Reference clock to half of the frequency of Reference clock using the control inputs S1 and S2 if Bank A is connected to feedback FBK. In addition, using the control inputs S1 and S2, the PI6C2308-6 allows bank A to switch from Reference clock to 2X the frequency of Reference clock if Bank B is connected to feedback FBK. For testing purposes, the select inputs connect the input clock directly to outputs.
Block Diagrams
/2 REF PLL MUX FBK CLKA1 CLKA2
Extra Divider (-3, -4)
CLKA3 CLKA4 /2 CLKB1
S2 S1
Select Input Decoding
Extra Divider (-2,-3)
CLKB2 CLKB3
PI6C2308 (-1, -1H, -2, -3, -4)
CLKB4
REF
PLL
MUX
S2 S1
Select Input Decoding /2 MUX
FBK CLKA1 CLKA2 CLKA3 CLKA4
Pin Configuration PI6C2308 (1, 1H, 2, 3, 4, 6)
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 16-Pin 13 W, L 12 11 10 9 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
PI6C2308-6
CLKB1 CLKB2 CLKB3 CLKB4
1
PS8384D
06/26/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 3.3V Zero Delay Buffer
Select Input Decoding for PI6C2308 (-1, -1H, -2, -3, -4)
S2 0 0 1 1 S1 0 1 0 1 CLKA [1-4] Hi- Z Driven Driven Driven CLKB [1-4] Hi- Z Hi- Z Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown Y N Y N
Select Input Decoding for PI6C2308-6
S2 0 0 1 1 S1 0 1 0 1 CLKA [1-4] Hi- Z Driven = Reference Driven = PLL Driven = PLL CLKB [1-4] Hi- Z Driven = Reference/2 Driven = PLL Driven = PLL/2 Output Source PLL Reference PLL PLL PLL Shutdown Y Y N N
Available PI6C2308 Configurations
D e vice PI6C2308- 1 PI6C2308- 1H PI6C2308- 2 PI6C2308- 2 PI6C2308- 3 PI6C2308- 3 PI6C2308- 4 PI6C2308- 6 PI6C2308- 6 Fe e dback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A Bank B Bank A Fre que ncy Reference Reference Reference 2X Reference 2X Reference 4X Reference 2X Reference Reference Reference or 2X Reference Bank B Fre que ncy Reference Reference Reference/2 Reference Reference 2X Reference 2X Reference Reference or Reference/2 Reference
2
PS8384D
06/26/01
REF - Input to CLKA/CLKB Delay (ps)
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 3.3V Zero Delay Buffer
Zero Delay and Skew Control
REF. Input to CLKA/CLKB Delay vs. Difference in Loading between FBK pin and CLKA/CLKB pins
800
600
400
200
0 -25 -200 -20 -15 -10 -5 0 5 10 15 20 25
-400
PI6C2308-1H
-600
-800
PI6C2308-1,2,3,4,6
-900
-1000
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
To close the feedback loop of the PI6C2308, the FBK pin can be driven from any of the 8 available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs.
Maximum Ratings
Supply Voltage to Ground Potential ...................0.5V to +7.0V DC Input Voltage (Except REF) .................. 0.5V to VDD +0.5V DC Input Voltage REF ................................................ 0.5 to 7V Storage Temperature ........................................ 65C to +150C Maximum Soldering Temperature (10 seconds) ................ 260C Junction Temperature ....................................................... 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................. >2000V
Operating Conditions
Parame te r VDD TA CL CIN
(Over operating range, TA = 0C to +70C, VCC = 3.3V 0.3V)
De s cription Supply Voltage Operating Temperature (Ambient) Load Capacitance Input Capacitance M in. 3.0 0 M ax. 3.6 70 30 7 Units V C pF
3
PS8384D
06/26/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 3.3V Zero Delay Buffer
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Signal REF(1) C LK A1(2) C LK A2(2) VDD GN D C LK B1(2) C LK B2(2) S2(3) S1(3) C LK B3(2) C LK B4(2) GN D VDD C LK A3(2) C LK A4(2) FBK C lock output, Bank A C lock output, Bank A 3.3V supply Ground C lock output, Bank B C lock output, Bank B Select input, bit 2 Select input, bit 1 C lock output, Bank B C lock output, Bank B Ground 3.3V, supply C lock output, Bank A C lock output, Bank A PLL feedback input D e s cription Input reference frequency, 5V tolerant input, allows spread spectrum clock input
Electrical Characteristics for Commercial Temperature Devices
Parame te r VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD IDD De s cription Input LOW Voltage(4) Input HIGH Voltage(4) Input LOW Current Input HIGH Current Output LOW Voltage(5) Output HIGH Voltage(5) VIN = 0V VIN = VDD IOL = 8mA (1, 2, 3,4, 6) IOL = 12mA (- 1H) IOH = 8mA (1, 2, 3,4, 6) IOH = 12mA (- 1H) REF = 0 MHz Unloaded outputs, 66.66 MHz, Select inputs at VDD or GND Unloaded outputs 100 MHz Select Inputs @ VDD or GND Te s t Conditions M in. 2.0 2.4 M ax. 0.8 50 100 0.4 V 12 39 54 mA A Units V A
Power Down Supply Current Supply Current Supply Current
4
PS8384D
06/26/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 3.3V Zero Delay Buffer
Switching Characteristics(5) for Commercial Temperature Device
Parame te rs t1 t2 N ame O utput Frequency Duty C ycle(5) = t2 / t1 (2308- 1H) Duty C ycle = t2 / t1 (2308- 1, - 2, - 3, - 4, - 6) Rise Time(4) @30pF t3 Rise Fall t4 Time(4) Time(4) @ 15 p F Measured between 0.8V and 2.0V Rise Time(4) @30pF (1H) @ 30pF Fall Time(4) @15pF Fall Time(4) @30pF (1H) O utput to O utput on same bank (23081,1H,2,3,4,6) t5 O utput Bank A to O utput Bank B Skew(4) (23081,1H,4) O utput Bank A to O utput Bank B Skew(4) (23082,3,6) t6 (Phase Error) t7 t8 Skew(4) All outputs equally loaded, VDD/2 All outputs equally loaded, VDD/2 All outputs equally loaded, VDD/2 0 0 1 200 10 0 400 1. 0 ms ps Te s t Conditions 15pF to 30pF load Measured at 1.4V, for high drive output Measured at 1.4V, for normal drive output M in. 10 45 40 50 50 Typ. M ax. Units 134 55 60 2. 2 1. 5 1. 5 2. 2 1. 5 1. 2 5 200 200 400 200 600 V/ns ps ns % MHz
Input to O utput Delay, REF Rising Edge Measured at VDD/2 to FBK Rising Edge(4) Device to Device Skew(4) O utput Slew Rate(4) Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2.0V on 1H device using Test C ircuit #2 Measured at 66.67 MHz, loaded 30pF outputs Measured at 133 MHz, loaded 15pF outputs Measured at 66.6 MHz, loaded 30pF outputs Stable power supply, valid clocks presented on REF and FBK pins
tJ
C ycle- to- C ycle (23081,1H,4)
Jitter(4)
tJ tLO CK
C ycle- to- C ycle Jitter(4) (23082,3,6) PLL Lock Time(4)
Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. REF and FBK inputs have a threshhold voltage of VDD/2. 5. For definition of t1-8, see Switching Waveforms on page 8.
5
PS8384D
06/26/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 3.3V Zero Delay Buffer
Operating Conditions for Industrial Temperature Devices
Parame te r VDD TA CL CIN Supply Voltage O perating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance D e s cription M in. 3.0 40 M ax. 3.6 85 30 15 7 pF Units V C
Electrical Characteristics For Industrial Temperature Devices
Parame te r VIL VIH IIL IIH VOL VOH IDD (PD mode) D e s cription Input LO W Voltage Input HIGH Voltage Input LO W Current Input HIGH Current O utput LO W Voltage(4) O utput HIGH Voltage(4) Power Down Supply Current VIN = 0V VIN = VDD IOL = 8mA (1,2,3,4,6) IOL = 12mA (1H) IOL = 8mA (1,2,3,4,6) IOL = 12mA (1H) REF = 0 MHz Unloaded outputs, 100 MHz, Select inputs at VDD or GND Unloaded outputs, 66 MHz, REF, except (1H) Unloaded outputs, 33 MHz, REF, except (1H) 2.4 25.0 54.0 70.0 (1H) 39.0 20.0 mA A 2.0 50.0 100.0 0.4 V Te s t Conditions M in. M ax. 0.8 Units V A
IDD
Supply Current
6
PS8384D
06/26/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 3.3V Zero Delay Buffer
Switching Characteristics for Industrial Temperature Devices(5)
Parame te r t1 Name Output Frequency Te s t Conditions 30pF load, All devices 20pF load, 1H devices 15pF load, 1,2,3,4,6 devices Duty Cycle(4) = t2 / t1 (1,2,3,4,6) t2 Duty Cycle(4) = t2 / t1 (1H) Measured at 1.4V, FOUT <66.66MHz 30pF load Measured at 1.4V, FOUT <133 MHz 15pF load Measured at 1.4V, FOUT <45 MHz 15pF load Measured at 1.4V, FOUT <66.66MHz 30pF load Measured at 1.4V, FOUT <133 MHz 15pF load Measured at 1.4V, FOUT <45MHz 30pF load t3 Rise Time(4) (1,2,3,4) Rise t4 Time(4) (1H) (1,2,3,4) (1H) Measured between 0.8V and 2.0V, 30pF load Measured between 0.8V and 2.0V, 15pF load Measured between 0.8V and 2.0V, 30pF load Measured between 0.8V and 2.0V, 30pF load Measured between 0.8V and 2.0V, 15pF load Measured between 0.8V and 2.0V, 30pF load 40.0 45.0 45.0 40.0 45.0 50.0 10 M in. Typ. M ax. 100 134 134 60.0 55.0 60.0 55.0 2.2 1.50 1.50 2.50 1.50 1.25 200 ps ns % MHz Units
Fall Time(4) Fall Time(4)
Output to Output Skew on same Bank (1,2,3,4,6)(4) t5 Output Bank A to Output Bank B All outputs equally loaded Skew (1,1H, 4) Output Bank A to Output Bank B Skew (2, 3,6) t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge(4) Device to Device Skew(4) Output Slew Rate(4) Cycle to Cycle Jitter(4), (1, 1H, 4) Cycle to Cycle (2,3,6) Jitter(4), Measured at VDD/2 Measured at VDD/2 MHz, on the FBK pins of devices Measured twx 0.8V & 2.0V on 1H,5 device using Test Crt #2 Measured at 66.67 MHz, loaded outputs, 30pF Load Measured at 133 MHz, loaded outputs, 15pF Load Measured at 66.67 MHz, loaded outputs, 30pF Load Stable power supply, valid clocks presented on REF & FBK pins 1 0
400 200 600
V/ns 200 100 400 1.0 ms ps
tJ
tLOCK
PLL Lock Time(4)
Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. REF and FBK inputs have a threshhold voltage of VDD/2. 5. For definition of t1-8, see Switching Waveforms on page 8.
7
PS8384D
06/26/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 3.3V Zero Delay Buffer
Switching Waveforms
Duty Cycle Timing
t1 t2
1.4V 1.4V 1.4V
All Outputs Rise/Fall Time
2.0V OUTPUT 0.8V 2.0V 0.8V 0V 3.3V
t3
t4
Output-Output Skew
OUTPUT
1.4V
OUTPUT
1.4V
t5
Input-Output Propagation Delay
INPUT
VDD/2
FBK
VDD/2
t6
Device-Device Skew
FBK Device 1
VDD/2
FBK Device 2
VDD/2
t7
Test Circuit #1
0.1mF
VDD OUTPUTS CLK out CLOAD
Test Circuit #2
0.1mF
VDD OUTPUTS 1kW 1kW CLK out 10pF
0.1mF
VDD GND GND
0.1mF
VDD GND GND
Test Circuit for all parameters except t 8
Test Circuit for t 8 ,Output slew rate on -1H device
8
PS8384D
06/26/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 3.3V Zero Delay Buffer
16-Pin SOIC (W)
16
.149 .157
3.78 3.99 .0099 .0196 0.25 x 45 0.50
1 .386 .393 9.80 10.00 .0155 .0260 0.393 0.660 REF .053 .068 1.35 1.75 SEATING PLANE 0-8 0.41 1.27 .016 .050 .0075 .0098 0.19 0.25
.2284 .2440 5.80 6.20
.050 BSC 1.27
.013 .020 0.330 0.508
.0040 0.10 .0098 0.25
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
16-Pin TSSOP (L)
16
.169 .177
4.3 4.5
1 .193 .201 4.9 5.1 .004 .008 .047 max. 1.20 SEATING PLANE 0.45 .018 0.75 .030 .252 BSC 6.4
0.09 0.20
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS
Note: Controlling dimensions in millimeters. Ref: JEDEC MS - 012 AC
9
PS8384D
06/26/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308 3.3V Zero Delay Buffer
Ordering Information (Commercial Temperature Device)
Orde ring Code PI6C2308- 1W PI6C2308- 1HW PI6C2308- 2W PI6C2308- 3W PI6C2308- 4W PI6C2308- 6W PI6C2308- 1L PI6C2308- 1HL L16 16- pin TSSO P W16 16- pin 150- mil SOIC Commercial Package Name Package Type Ope rating Range
Ordering Information (Industrial Temperature Device)
Orde ring Code PI6C2308- 1WI PI6C2308- 1HWI PI6C2308- 2WI PI6C2308- 3WI PI6C2308- 4WI PI6C2308- 6WI PI6C2308- 1LI PI6C2308- 1HLI L16 16- pin TSSO P W16 16- pin 150- mil SOIC Industrial Package Name Package Type Ope rating Range
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
10
PS8384D 06/26/01

▲Up To Search▲

Price & Availability of PI6C2308

	To Download PI6C2308 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .